• 专利附录
  • 专利说明
  • 权利要求
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    • 专利摘要:
    PURPOSE: A method for etching insulation layer and a method for fabricating semiconductor elements are provided to scavenge a free fluorine by a carbon monoxide with no longer present to allow the further breakup of the octofluorobutene into excessive amounts of free fluorine. CONSTITUTION: Manifold etching can be used for insulating layers(114,400,422,426). In the example of one group, the insulation layers(114,400,422,426) are etched using an oxide etching component, a fluorescent scavenging component and an organic etching component. In another example of a set, the insulating layers(114, 400, 422,426) comprise at least 1 atomic weight % of carbon or hydrogen. The insulation layers are etched using oxide etching gas and gas containing nitrogen. In another of a different group, the insulation layers(114, 400, 422,426) are formed on a semiconductor element substrate(100) having a diameter of about 300 millimeters. The insulation layers(114, 400, 422,426) are etched by using oxide etching gas and a gas containing nitride.
    公开号:KR20010030088A
    申请号:KR1020000046909
    申请日:2000-08-14
    公开日:2001-04-16
    发明作者:라자고팔란가네시
    申请人:비센트 비.인그라시아, 알크 엠 아헨；모토로라 인코포레이티드；
    IPC主号:
    专利说明:

    Process for etching an insulating layer and forming a semiconductor devices
    Technical field of invention
    The present invention generally relates to a method for forming semiconductor devices, in particular an etching method used to form semiconductor devices.
    Related technology
    Modern semiconductor devices are using more low-k dielectric materials in interlevel dielectrics to improve performance and reduce problems such as cross talk, unintended capacitance between conductors, and the like. Materials used for low-k dielectrics typically include polymer films or a film based on silica. As used herein, low-k dielectrics are dielectrics having a relative dielectric constant no greater than about 3.5. Silicon dioxide has traditionally been used as a dielectric material and has a relative dielectric constant of about 3.9. When etching a material based on silica typically, the etching process stops at an etch-stop layer such as silicon nitride, silicon rich silicon nitride or other similar materials.
    Newer low-k dielectrics based on silica include fluorine-doped oxides and oxides containing carbon and hydrogen. Etching these silica-based low-k materials is particularly difficult when hydrogen or both carbon and hydrogen are present in the silica-based film. When etching these materials, they need to be selectively etched into silicon nitride. Otherwise, formation of an electrical short or metal films (copper or aluminum) in self-aligned contacts may occur.
    Traditional silicon dioxide etching processes do not work well, especially for silica based organic film (OSG). In general, octofluorobutene (C 4 F 8 ) and carbon monoxide (CO) have been used to etch silicon dioxide films selective to silicon nitride. However, this etching chemistry will not be able to efficiently etch carbon and hydrogen present in the OSG film. Molecular nitrogen (N 2 ) has been added to trifluoromethane (CHF 3 ) and carbon tetrafluoride (CF 4 ) gases while etching the oxide. In this particular example, the ratio of nitrogen to total fluorocarbon mixture is considered to be approximately 1: 2. This chemistry has been tailored specifically for high aspect ratios for traditional oxides (much less than one atomic percent hydrogen or carbon levels). The level of nitrogen present may not be sufficient to remove hydrogen or carbon that appears to be dielectrics of silica based organics.
    BRIEF DESCRIPTION OF THE DRAWINGS The present invention has been described by way of example and is not limited to the accompanying drawings, in which like numerals represent like elements.
    Those skilled in the art will appreciate that the elements of the various figures are shown for simplicity and clarity and need not be drawn to scale. For example, the dimensions of some of the elements shown in the figures may be exaggerated relative to other elements to help improve understanding of embodiments of the present invention.
    1 is a partial cross-sectional view of a semiconductor device after forming gate electrodes and a low-k dielectric material.
    FIG. 2 is a sectional view of the substrate of FIG. 1 after etching the contact opening. FIG.
    3 is a cross-sectional view of the substrate of FIG. 2 after forming a conductive plug in the opening.
    4 is a cross-sectional view of the substrate of FIG. 3 after forming wiring and another set of interlevel dielectric layers.
    Figure 5 is a cross sectional view of the substrate of Figure 4 after forming via openings for dual inlaid openings.
    FIG. 6 is a cross-sectional view of the substrate of FIG. 5 after forming a dual inlaid opening. FIG.
    Figure 7 is a cross sectional view of the substrate of Figure 6 after forming a substantially completed device.
    Explanation of symbols on the main parts of the drawings
    100 substrate 102 doped region
    104: dielectric layer 108: capping layer
    110: liner layer 112: sidewall spacer
    114: insulation layer
    details
    Many variations can be used to etch the insulating layers. In one embodiment, the insulating layer is etched using an oxide etching component, a fluorine removal component, and an organic etching component. In another embodiment, the insulating layer comprises at least one atomic weight percent carbon or hydrogen. The insulating layer is etched using an oxide etching gas and a nitrogen containing gas. In yet another form of embodiment, an insulating layer is formed over a semiconductor device substrate having a diameter of at least about 300 mm or more. The insulating layer is etched using an oxide etching gas and a nitrogen containing gas. The invention is defined by the claims, and will be better understood from the following detailed description of the embodiments.
    1 is a cross-sectional view of a semiconductor device in the middle of a process. In FIG. 1, the semiconductor device substrate 100 includes doped regions 102 that are source, drain, or source / drain regions. As used herein, semiconductor device substrates include single crystal semiconductor wafers, semiconductor-on-insulator wafers, or any other substrate used to form a semiconductor device. The semiconductor device substrate has a diameter of approximately 200 mm, for example, although a size of 300 mm or larger can be used. The gate dielectric layer 104 covers the semiconductor device substrate 100 and a portion of the region 102. The gate electrode layer 106 covers the gate dielectric layer 104, and the capping layer 108 covers the gate electrode 106. Typically, the capping layer 108 includes silicon nitride or other similar material. After forming these elements, a liner layer 110 is formed over the doped regions and the gate electrode stack portion. The liner layer is typically an oxide. The sidewall spacers 112 are formed along the vertical sidewall portion of the gate electrode structure adjacent next to the liner layer 110. In this embodiment, the sidewall spacers 112 are made of silicon nitride.
    A first interlevel dielectric layer 114 is then formed on the liner layer 110 and the spacers 112. The first interlevel flow layer 114 is typically a material based on hydrogen or silica containing any one of carbon and hydrogen. Typically the atomic weight percent of hydrogen or hydrogen and carbon is at least about 5 atomic percent and may be as high as about 20 atomic percent. Etching of silica based films at this level is quite different from traditional silicon dioxide films. Although oxides based on tetraethylorthosilicate-based (TEOS-based) include carbon and hydrogen, silicon dioxide films formed from TEOS will be much smaller than the atomic percent carbon and hydrogen composition in the film. . Therefore, membranes based on organic silica are within them much higher levels of hydrogen and carbon, for example approximately 5 to 20 atomic percent hydrogen or bonded hydrogen and carbon. When only hydrogen is added, the relative dielectric constant of this film is typically in the range of approximately 2.7 to 3.5. If both carbon and hydrogen are added up to about 10 atomic percent, the relative dielectric constant is in the range of approximately 2.5 to 2.8. The first ILD layer 114 may be formed by spin-on or chemical vapor deposition. After the planarized interlevel dielectric layer ILD is formed, a capping layer 116 is typically formed overlying it. The capping layer 116 is typically a silicon dioxide film, but other films may be used as needed. Thereafter, the photoresist layer 120 is formed and patterned at the place where the contact opening is to be formed.
    Etching is performed to remove portions of the capping layer 116, the first ILD layer 114, and the liner layer 110 to form a contact opening 20 as shown in FIG. 2. The etching chemistry used to etch the first ILD layer 114 typically includes at least one type comprising carbon and fluorine (fluorine carbide species). Such etch species is the main oxide etchant component for silica in low-k dielectric materials. In addition, the etch chemistry includes a fluorine removal component to improve the selectivity of the nitride and organic etchant, which is used to etch carbon and hydrogen in the first ILD layer. In one particular embodiment, the chemistry may comprise octofluorobutene (C 4 F 8 ) as silica etchant, carbon monoxide (CO) as fluorine removal component and molecular nitrogen gas as organic etching component. CO helps to raise selectivity for nitride and nitrogen gases that react with carbon and hydrogen to form hydrogen cyanide (HCN), which is released as a gas.
    The first ILD layer 114 has the ability to selectively etch silicon nitride in both the capping layer 108 and the sidewall spacers 112 so that relatively small (unimportant) portions are removed. The selectivity of oxide: nitride to be removed using this etching is typically at least 5: 1, and more generally in the range of about 6: 1 to 25: 1. In one specific embodiment, octofluorobutene flows at approximately 10 standard cubic centimeters per minute (sccm), carbon monoxide flows at about 400 sccm, and molecular nitrogen gas flows at about 100 sccm. In this particular embodiment, this gas flow rate is used for a 200 mm diameter wafer. If wafers of different sizes are used, the flow rate will generally need to be adjusted. A simple conversion may be to take the size of the diameter of the substrate to be etched divided by 200 and then power up within the range of approximately 1.5 to 2.5. In this way the gas flow rate can be adjusted for various wafer sizes.
    In another embodiment, the carbon monoxide flow can be adjusted to about 100 sccm and the nitrogen flow can be kept constant at about 100 sccm. In yet another embodiment, the flow rates of carbon monoxide and nitrogen can be increased outside the stated range. When the flow rate of carbon monoxide is about 500 standard cubic centimeters per minute and nitrogen is about 200 standard cubic centimeters per minute, etch selectivity as high as 25: 1 can be achieved. Higher selectivity is possible with better optimization of gas flow rates.
    The gas ratio of nitrogen gas to octofluorobutene is typically at least about 1: 1, more generally in the range of about 5: 1 to 20: 1. Expressed in the gas ratio of carbon monoxide to molecular nitrogen, gas flow rates of 1 part carbon monoxide to 1 part nitrogen gas up to at least 4: 1 are preferred. In general, selectivity improves as the amount of carbon monoxide increases. However, if the relative amount of nitrogen is reduced too much with respect to carbon monoxide, some of the hydrocarbon etching seen by the use of nitrogen gas may decrease. Therefore, although the lower limit of the carbon monoxide to nitrogen ratio is unknown, there is a problem that etching the hydrocarbon will be too slow. In addition to the gas flow rate, it can be expected that all other etch parameters will have the same parameters commonly used in this industry.
    Other silica containing species may be used. Ideally, the silica etch species does not have a hydrogen atom. Examples are carbon tetrafluoride (CF 4 ), hexafluoroethane (C 2 F 6 ), hexafluoropropene (C 3 F 6 ), and octofluoropentadiene (C 5 F 8 ). In addition, the silica etched species may include some hydrogen, such as trifluoromethane (CHF 3 ).
    In another embodiment, if the nitride layers 108 and 112 are substantially sufficiently thick, carbon monoxide may not be needed to etch the ILD layer 114. In these specific embodiments, only fluorocarbon etch species and molecular nitrogen may be used. In this case, the ratio of fluorocarbon to nitrogen should be at least 1: 1, and will typically range from 5 parts nitrogen gas to 1 part fluorocarbon to about 20 parts nitrogen gas to 1 part fluorocarbon. In yet another embodiment, one or both of carbon monoxide and nitrogen gas may be replaced with nitrogen oxides. If nitrogen oxide is used, it can be a fluorine remover similar to carbon monoxide. Since N must be present when N 2 O is blocked, the nitrogen in the plasma can be an organic etchant that reacts with carbon and hydrogen in a silica-based material.
    Although not disclosed, each of these given etch chemistries will typically also include noble gases such as argon, helium, neon, and the like. Process chamber dynamics show that inert gases help control chamber pressure, correct residence time, and improve etch rate uniformity.
    Capping layer 116 and oxide liner layer 110 may be etched using the same etch chemistry used to etch first ILD layer 114, or may be etched using more traditional oxide etch chemistry.
    In yet another embodiment, many steps may be performed to create the contact opening 20. In one embodiment, a suitable fluorocarbon paper capping layer 116 and a majority of the first ILD layer 114 can be used in combination with nitrogen, after which the process is low to terminate the etching. Conversion to selective chemistry, which may include fluorine to carbon ratio gas, nitrogen, and carbon monoxide.
    Thereafter, a contact plug 30 is formed in the contact opening as shown in FIG. Contact plugs are formed using barrier film 32 and conductive fill material 34. In one particular embodiment, barrier film 32 includes titanium, titanium nitride, tantalum, tantalum nitride, other refractory metals, nitrides corresponding thereto, or a combination thereof. Conductive filler material 34 is typically tungsten, but in some embodiments aluminum or possibly copper may also be used. The first interconnect level is formed by forming a second ILD layer 400 and forming interconnect trenches that contact the conductive plugs, as shown in FIG. The second ILD layer 400 is typically formed of a material similar to the first ILD layer 114. After etching the second ILD layer 400 using any one of the described etching conditions to etch the first ILD layer 114, the interconnected trenches may include the barrier film 412 and the conductive fill material 414. Filled with. After polishing, interconnect 410 is formed as shown in FIG. The barrier film 412 may be one or more of the materials described with respect to the barrier film 32. In this particular embodiment, the conductive fill material 414 is typically copper, aluminum, tungsten, or the like.
    The second film set is formed to make dual inlaid openings to be formed. The nitride capping layer 420 is formed to retain the copper 414 in the interconnect 410. A third ILD layer 422, an etch-stop layer 424, a fourth ILD layer 426, and a capping layer 428 are sequentially formed. Capping layer 428 is similar to capping layer 116 as described in connection with FIG. 1. Interlevel dielectric layers 422 and 426 are similar to those described with respect to first interlevel dielectric layer 114. Typically, layers 420 and 424 are insulating layers. The etch-stop layer 424 is typically formed of a nitride layer such as silicon nitride, and the capping layer 420 is also formed of silicon nitride or the like. Thereafter, the photoresist layer 430 is formed and patterned to correspond to the via portion of the dual inlaid opening.
    Referring to FIG. 5, etching is then performed to create the via portion 52 extending through the layers 422-428. Etching stops on capping layer 420 to prevent possible via veil formation. The via film may be formed if the plasma etch chemistry used to form the via portion 52 can extend to contact the conductive fill material 414. The etch chemistry already described with respect to the first ILD layer 114 may be used for the etch layers 422, 426. The etch chemistry will change when etching through the nitride etch-stop layer 424 and may change before reaching the capping layer 420.
    After removing the photoresist layer 430, another photoresist layer 64 is formed over the capping layer 428 and patterned to match the interconnect opening. Referring to FIG. 6, etching is then performed to form the dual inlaid interconnect openings 60, the dual inlaid interconnect openings comprising interconnect trench portions 62 and via portions 52. Etching will typically be performed to remove the capping layer 428 and the fourth ILD layer 426 and stop on the etch-stop film 424. The next portion of the etch uses a nitride etch chemistry to remove both the etch-stop film 424 and the capping layer 420 in the dual inlaid opening. Since etching of the capping layer 420 and the etch-stop layer 424 is performed at a lower power compared to oxide etching, the possibility of via film formation is reduced.
    The process continues to form a substantially complete device such as that shown in FIG. First, barrier film 72 is formed, followed by conductive fill material 74. Materials described for use in connection with interconnect 410 may be used at this level. A polishing step is used to remove portions of the film 72 and material 74 that lie outside of the dual inlaid openings. This forms the interconnect 70 as described in FIG. Passivation layer 76 is then formed on the best level of interconnect to form a substantially completed device.
    Various embodiments of the present invention include many advantages. One of the biggest advantages is that it allows for an ideal etch rate for organic-containing materials based on silica to low-k dielectrics. The combination of fluorocarbon and nitrogen containing etch chemistry allows etching of silica and hydrocarbons. In addition, fluorine from fluorocarbons etch silicon dioxide, and the nitrogen containing material allows etching of hydrocarbon materials in low-k dielectric materials. The addition of carbon monoxide aids in selectivity to other material layers, especially silicon nitride. Carbon monoxide is thought to remove free fluorine in the plasma that will aid selectivity. In particular, when compounds such as octofluorobutene are used, the plasma can generate both free fluorine and carbon-fluorine polymers. Carbon monoxide aids in the removal of free fluorine, while allowing the fluorocarbon polymer in the plasma to become a passivating agent.
    In general, the oxygen released during etching the silica containing material helps to release the free fluorine needed to continue etching the silica containing component of the film. However, since oxygen is not introduced as a separate species, only oxygen present in the plasma will be the oxygen released during etching the silica containing component of the material. When the nitride layer is etched, oxygen will not be released. Therefore, carbon monoxide removes the free fluorine present and there is no longer any oxygen that can allow further separation of the octofluorobutene into excess amounts of free fluorine.
    In the foregoing description, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the following claims. The description and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention.
    The above advantages, other advantages, and solutions to problems have been described above in connection with specific embodiments. However, the above advantages, advantages, solutions to problems, and any factors that give rise to or clarify the advantages, advantages, or solutions are important, necessary, or fundamental of any one or all of the following claims. It is not to be interpreted as a feature or element. As used herein, terms such as "comprises" or "comprising", or variations thereof, are intended to include other elements, and thus include a list of elements. Processes, methods, articles, or apparatuses do not include only their elements, and although not explicitly listed, may include other elements or elements inherent to the process, method, article, or apparatus.
    The present invention provides an insulating layer etching method that solves the problems of the prior art, where it was difficult to etch silica based low-k materials when hydrogen or both carbon and hydrogen were present in the silica based film.
    权利要求:
    Claims (5)
    [1" claim-type="Currently amended] In the insulating layer 114, 400, 422, 426 etching forming method,
    Forming an insulating layer 114, 400, 422, 426 on the substrate 100, and
    Etching the insulating layer (114, 400, 422, 426) using an oxide etching component, a fluorine removal component, and an organic etching component.
    [2" claim-type="Currently amended] In the insulating layer 114, 400, 422, 426 etching forming method,
    Forming an insulating layer 114, 400, 422, 426 on the substrate 100,
    The insulating layers 114, 400, 422, and 426 include carbon and hydrogen,
    Forming an insulating layer over the substrate, wherein the sum of the atomic percent of hydrogen and atomic percent of carbon is in the range of approximately 5 to 20 atomic percent, and
    Etching the insulating layer (114, 400, 422, 426) using an oxide etching component, a fluorine removal component, and an organic etching component.
    [3" claim-type="Currently amended] In the insulating layer 114, 400, 422, 426 etching forming method,
    Forming an insulating layer 114, 400, 422, 426 on the substrate 100, and
    Etching the insulating layer 114, 400, 422, 426 using an oxide etching component, a fluorine removal component, and an organic etching component,
    The oxide etching component is a fluorine carbide material,
    The fluorine removal component is carbon monoxide,
    And the organic etch component is molecular nitrogen.
    [4" claim-type="Currently amended] In the insulating layer 114, 400, 422, 426 etching forming method,
    Forming an insulating layer 114, 400, 422, 426 on the substrate 100,
    The insulating layer 114, 400, 422, 426 comprises at least one atomic weight percent of an element selected from the group consisting of carbon and hydrogen, and
    Etching the insulating layer (114, 400, 422, 426), wherein the etching is performed using an oxide etching gas and a nitrogen containing gas.
    [5" claim-type="Currently amended] In the method of forming a semiconductor device,
    Forming insulating layers 114, 400, 422, 426 on a semiconductor device substrate 100 having a diameter of at least about 300 mm, and
    Etching the insulating layer (114, 400, 422, 426) using an oxide etching gas and a nitrogen containing gas.
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    同族专利:
    公开号 | 公开日
    EP1085563A3|2001-09-19|
    SG93886A1|2003-01-21|
    CN1163951C|2004-08-25|
    CN1288253A|2001-03-21|
    TW455948B|2001-09-21|
    EP1085563A2|2001-03-21|
    JP2001110792A|2001-04-20|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1999-09-13|Priority to US39451799A
    1999-09-13|Priority to US9/394,517
    2000-08-14|Application filed by 비센트 비.인그라시아, 알크 엠 아헨, 모토로라 인코포레이티드
    2001-04-16|Publication of KR20010030088A
    优先权:
    申请号 | 申请日 | 专利标题
    US39451799A| true| 1999-09-13|1999-09-13|
    US9/394,517|1999-09-13|
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